Field of the Invention
The present invention relates to a method and a system for optimizing utilization of a programmable logic element for use in an electronic control unit for vehicles, wherein the programmable logic element has a soft CPU and/or an unused remaining area.
Description of the Background Art
The term electronic control unit is typically understood to mean a control system, for example a control unit in a motor vehicle. The electronic control unit can be used to measure, control, regulate, and/or calibrate vehicle components, for example. A vehicle can include, for example, watercraft, land vehicles, aircraft, spacecraft, and/or combinations thereof.
Conventional electronic control units for vehicles are implemented with techniques including the use of embedded systems, i.e. electronic computing units that are integrated in a technical context. A wide variety of CPU architectures are known for this purpose. An especially flexible platform in this context is highly integrated logic elements, e.g. field programmable gate arrays (FPGA), which not only reproduce various CPU architectures, but can also carry out parallel computing work well without a processor, through logic alone.
In this regard, the programmability of a logic element refers only secondarily to the specification of time sequences in the logic element. Primarily, this refers to the definition of fundamental functionalities of individual universal blocks in the programmable logic element and their interconnection to one another. Different circuits can be implemented in a programmable logic element through such programming of internal structures. These range from circuits of low complexity to highly complex circuits such as microprocessors. Since such a microprocessor is implemented/constructed exclusively through logic synthesis, it is called a soft CPU.
One example of such a soft CPU is the MicroBlaze™, the user documentation for which can be found at http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/mb_ref guide.pdf. However, the present invention is in no way limited to the MicroBlaze™, but instead can be used with any desired soft CPU.
Depending on the desired configuration scope, soft CPUs such as the MicroBlaze™ have a configurable three- to five-stage pipeline, internal cache, an interrupt, a hardware-based multiplier, and optionally a hardware-based divider, a floating-point unit and special shift register units as well as multiple different buses that are provided for connecting to a wide range of peripherals and memory in a programmable logic element.
In an area-optimized variant of the MicroBlaze™ that uses a three-stage pipeline, the clock frequency is reduced in favor of a reduced demand for logic area. This contrasts with the performance-optimized version, in which a five-stage pipeline is used, permitting clock rates up to 210 MHz, but which accordingly also requires a larger area.
Moreover, the soft CPU can be configured such that core processor operations that are used infrequently and are resource-intensive to implement on the hardware side are added to the soft CPU (e.g. multiplication, division, or floating-point operations).
The amount of freely programmable area of the logic element occupied by the soft CPU is a function of the configuration of the soft CPU. If the amount of freely programmable chip area of a programmable logic is not exhausted by a required configuration—with or without a soft CPU—for producing a specific command set for executable computing operations, portions of the programmable logic element remain unused. Within the scope of the present invention, the remainder of freely programmable chip area is therefore referred to as the unused remaining area of the programmable logic element.
Moreover, it is part of current practice in the development of electronic control units to perform model-based simulations to test specific control and regulation mechanisms for an electronic control unit as a function of the applicable stage of development. In so doing, the desired control and regulation functions are first reproduced in a model. Based on the model-based design, program code or software is then generated that implements the previously modeled function in accordance with the appropriate model variant. At an early stage of development, first the model and then the software are tested in what is called a model- and software-in-the-loop (MIL/SIL) simulation method in order to detect differences between the behavior of the model code and the program code/software. If the program code is also executed on a real processor core, one speaks of a processor-in-the-loop (PIL) method or simulation. These PIL simulations permit early detection of bottlenecks, errors, and processes that cannot be implemented. PIL simulations and the profiling data produced thereby are known in the prior art, and are described in detail in, e.g., the documentation of applicable programs for model-based software design such as, e.g., TargetLink.
In later stages of development, parts of the hardware that have already been implemented (for example, a real electronic control unit for a vehicle as an embedded system) are tested for correct functionality with the aid of model-based, simulated input signals in what is called a hardware-in-the-loop (HIL) method.
As the stage of development advances, the expense of test equipment and test execution increases and the flexibility of the application of the systems to be tested decreases. For this reason, it is desirable to match model-based design for control units with regard to hardware-based boundary conditions/circumstances at an early stage.